1. Field of Invention
The present invention relates to access operation for a large block flash memory. More particularly, the present invention relates to an access operation on a large block flash memory by a pipeline manner.
2. Description of Related Art
Nonvolatile memory chips, which include nonvolatile memory arrays, have various applications for storing digital information. One such application is capable of storing a large amount of digital information used by digital cameras, as replacements for hard disk within a personal computer (PC) and so forth. Nonvolatile memory arrays are comprised of various types of memory cells, such as NOR, NAND and other types of structures known to those of ordinary skill in the art. One of the characteristics of nonvolatile memory is that the stored information still remains while power is disconnected or disrupted.
FIG. 1 is a block diagram, schematically illustrating architecture of flash memory card. In FIG. 1, the host end 90 can access data stored in a flash disk 100, in which the flash disk (memory device) 100 includes a controller 102 and a flash memory array 104. The flash memory array 104 may include one or more memory chips. In access operation, the host end 90 usually accesses the data in the flash memory array 104 via the controller 102 at the requested address. In addition to communicating with the host, the controller 102 also takes responsibility of managing the flash memory array 104 via the accessing interface 106. The flash memory storage device 100 is then configured as a drive by the host.
FIG. 2 is a mapping architecture maintained by the control unit. The host side, such as a drive, includes a plurality of logical blocks at the logical space 110, each of which blocks can be addressed by the host. Namely, the host can access all the logical space 110, including logical block 0, logical block 1, . . . , and logical block M−1. Also and the physical space 112 is used to store the actual information. The structure is conventional and can be understood by the skilled artisans.
A flash memory device generally is divided into a plurality of storage units, such as blocks which include page or more pages. As shown in FIG. 2, the physical space 112 of the flash memory device includes physical block 0, physical block1, . . . , and physical block N−1. The logical space 110 used by the host is always less than the physical space 112 because some of the physical blocks may be defective or used by the controller 102 for managing the flash memory module. One task of the controller 102 is to create the logical space 110 for host access. Indeed, the host 90 can not directly address the physical space 112, so that the controller 102 must maintain the mapping relations between the logical blocks and the physical blocks. Such a mapping information is always called as a mapping table and can be stored in the specific physical blocks or loaded into the SRAM within the controller. If a host 90 asks for accessing a particular logical block, the controller 102 then looks up the mapping table for identifying which physical block to be accessed.
FIG. 3 is a drawing, schematically illustrating the block structure of a conventional small block flash memory. A physical block X 114 includes 32 pages(sectors) for storing the host data of logical sector LBA0˜31 and their accompanying extra information.
FIG. 4 is a block diagram, schematically illustrating the conventional controller. There are two independent SRAM buffers 204 and 206 serving as the bank 0 and bank 1, for data transfer. Wen one bank is transferring data with the host 202 other bank can also transfer data with the flash memory array through the flash interface unit. A pipeline operation is used. The access operation is usually divided into three stages. The stage 1 represents that data is transferring between the host and the controller. Stage 2 represents that a calculation about which page (sector) to be written. Stage 3 represents that data is transferring between the controller and the flash memory, wherein a start program command, such as “10H” is conventionally also issued to the flash memory. Since there are two buffers 204 and 206 in the controller, they are alternatively used under the design of a pipeline manner. However, once the start program command is sent, the flash memory needs a long busy time, about 200 μs, to finish programming operation.
FIG. 5 is a drawing, schematically illustrating the block structure of large block flash memory. Because one page size is 2K+64 Bytes, there are four sectors (528 bytes*4) within one page for storing four logical sectors (512 bytes*4) and their extra information (16 bytes*4), such as error check code (ECC) etc.
When the conventional access operation is applied to the large block flash memory, one page needs four operations with respect to four sectors in transferring data. Since each time of the start program command consumes about 200 microseconds to actually program the flash memory. The operation speed is rather slow. In order to speed up the operation to program the large block flash memory, it needs a novel access manner.